https://www.nextplatform.com/2021/11/12/amd-gets-inside-facebooks-latest-and-most-powerful-microserver/ In-depth coverage of high-end computing at large enterprises, supercomputing centers, hyperscale data centers, and public clouds. Fri, 17 Dec 2021 16:53:38 +0000 hourly 1 https://wordpress.org/?v=6.7.1 https://www.nextplatform.com/2021/11/12/amd-gets-inside-facebooks-latest-and-most-powerful-microserver/#comment-172679 Fri, 17 Dec 2021 16:53:38 +0000 https://www.nextplatform.com/?p=139626#comment-172679 I think you have the details of the Milan part wrong. The I/O is all on one chiplet, so the six DDR4 DIMMs probably indicate a physical limitation. The same applies to all of the reduced I/O limits. There are several ways that AMD could scatter 36 cores across up to eight chiplets. Four chiplets only provide 32 cores, so at least five are needed. I’m guessing though that there are six Zen 3 chiplets with two cores on each disabled. That makes for a nice symmetric system and allows AMD to use harvested chips with some defects. I don’t know if it is possible to harvest I/O chiplets with single-point failures, but that also might explain some of the I/O restrictions.

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