No That’s a Zen/Zeppelin DIE that’s used for Epyc/Naples(4 Zen/Zeppelin SOC DIEs on an MCM) and Ryzen is a brand name for a consumer line of processors made from various Binned Zen/Zeppelin Server SOC DIEs(1 die for Ryzen-1 and 2 dies for Threadripper-1), with some of the server parts disabled. And I really suspect that the NextPlatform is an American publication now because any British Publication would take the time to get the AMD nomenclature correct. So that “Chiplet” is not called Ryzen and it’s Fabbed on a 14nm GF(Licensed from Samsung) process node and has been coming off GF’s diffusion lines at a better than 80% usable Die/Wafer yield rate.

AMD’s first generation Zen/Zeppelin DIE was first and formost designed for server usage with the top 5% going towards Epyc 7000 series production with any Zen/Zeppelin dies that could not make the grade being binned for consumer usage(Ryzen-1 and Threadripper-1 SKUs).

It should be noted that the 2nd generation Ryzen-2(Consumer) and Threadripper-2(Consumer HEDT) SKUs are obtained from a New Zen+(Minimal Tweaking of the Zen CPU Core/Uncore) Die(8 total Cores/2 CCX Units) on GF’s 12nm process while first generation Zen/Zeppelin(8 total cores/2 CCX units) Die is still produced using that 14nm(Licensed from Samsung Process) for any current/continuing first generation Zen Epyc/Naples production. And it sure took long enough to get the first generation 14nm Zen Epyc/Naples SKUs Vetted/Certified for production server workloads.

Zen2 on TSMC’s 7nm node, well that’s really the new CPU microarchitectural update that going to produce a much larger IPC gain. There are rumors of an at least 15% gain in Zen2 IPC over Zen1 and most likely for the server market a little higher clocks at a much greater power/thermal efficiency. That “Zen+” spin(New Stepping on a new Less than Half Node shrink really) is just for the consumer market on an interim basis for a little higher clock speed/fixed latency issue and higher DIMM/DRAM memory clocks(beyond JEDEC standards) supported for the consumer/gaming market. GF’s 12nm node did have some Transistor Tweaking for better leakage and gate resistance metrics but nowhere near what TSMC’s 7nm is expected to provide on that full node shrink.

Now for Zen2 and Epyc/Rome there is also talk of greatly increased L3 cache sizes and probably some new L1$ and L2$ allotments also, but there is also speculation on maybe 8 smaller Zen2/Zeppelin Dies(NON SOC), still at 8 cores each, surrounding a large central SOC die that provides the Memory Controllers and other off module services(SOC services die part on the MCM on Zen2/Epyc-2 SKUs). But that’s just some wild speculation on a possible new Epyc/Rome Die/Fabric topology that hopefully will be put to rest(Pro or Con) on Oct 6 at AMD’s yearly Investor Update event. PCIe 4.0 support would be a big plus for Epyc/Rome and I’d assume that would be compatable with current Epyc/SP3 MB’s PCIe PHY but I’m no expert on MBs or PCIe. So whatever the rumors concerning Zen2 Epyc/Rome(2nd generation Epyc) there is plausable speculation of 48 or 64 cores per Epyc/Rome MCM and more cores and threads all around that has made Intel feel the need to match on some level of at least 48 cores, on paper, until the hardware actually arrives as a product that’s certified/vetted for production server workloads, a long and involved process for any CPU maker.

Also there are a line of “P” branded Epyc 7000 series parts that are for single socket usage that do not do a take-over on any PCIe lane PHY, but at least the total numbers of available PCIe 3.0 lanes remains 128 across any EPYC/SP3 MB platform, be it 1P or 2P, as AMD does not currently segement on PCIe lane counts like Intel does.

So Intel is now grown fond of that Glue but still only two of those larger dies that will still come in at rather poor die/wafer yields and Intel’s binning operation has got to be one of the most complex in the industry what with all the product segementation that Intel engages in.

Now Intel is out with news on this new SKU(release date some time in 2019) and some more of that marketing spin that’s really needing the fine print made larger for folks with 20 20 to be able to read. And of course the Dell Boy benchmarking from Intel that’s always in need of independent review.

But this is in fact Core Wars Episode 2, The Empire Glues 2 Death Stars together at a price sure to make a bean counter’s head go all planet Alderaan when the invoice arrives.

P.S.

I’m sure that there is a whole load of goodness for the consumer/gaming market to come from the Zen2 Micro-Arch on TSMC’s 7nm node but that’s not where the large Revenues and Hgher Gross Margins that AMD needs will be coming from. The consumer market is nice, do not get me wrong, but for CPUs in the consumer HEDT market, that’s where a Processor Business trys to some degree to make the best of those lower performing DIE binns that do not make the grade to be binned Epyc server grade parts, or Xeon for Intel’s CPU parts.

Even with first generation Ryzen Desktop 8 core mainstream Parts they also came from Binned Zen/Zeppelin server DIEs so AMD was killing 3 birds(server, HEDT, and mainstream desktop CPUs) with one stone with that fist generation Zen/Zeppelin Die economy of scale. And that’s what has allowed AMD to really compete price/performance wise with Intel these last few years. There are now first generation 8 core Ryzen branded SKUs on sale for what Intel wants to charge for a quad core i5 series SKUs. As AMD has aready moved on to using a Zen+/Ryzen-2(2000 series) second generation consumer Die based 8 core/lower core count line of CPU SKUs(also selling at below MSRP Currently). And all this while Intel’s processor shortage is sure helping Intel’s gross margins to remain in the mid 60% range in the short term but in the long term Intel’s market share numbers will suffer.

“Intel UPI uses a directory-based home snoop coherency protocol, which provides an operational speed of up to 10.4 GT/s” – https://software.intel.com/en-us/articles/intel-xeon-processor-scalable-family-technical-overview

Infinity Fabric links are just barely faster than UPI (10.6 GT/s vs 10.4 GT/s) when connected die to die or socket to socket. Though latency seems likely to favor Cascade Lake. It’s not accurate to say UPI links have more bandwidth than Infinity Fabric.