As for off-package proprietary SMP coherency protocols, why would anyone get rid of those? Far too much investment and infrastructure built around their continued use, at least until off-package coherency no longer makes sense which isn’t that far in the future (chiplet and wafer-scale processing are the future; personally, the wafer-scale solution you’ve highlighted before is the most interesting, innovative, and credible solution to date). For non-SMP solutions, expect technologies like NvLink to remain dominant. They’ll attach to application processors using PCIe and CXL for application control operations which can be (non-)coherent while continuing to perform 99% of the compute and storage access without involving the application processor.

Large shared memory pools? There are some application workloads where these make sense, but volume wise, they represent a very, very small percentage of the TAM (HPE’s Machine was interesting research, but it was clear from the start, that HPE never really committed to or perhaps had the wherewithal to deliver a viable product offering). In fact, if you look at the research published by various platform / cloud providers, there are very few single system image applications that require more than single-digit TiB memory capacities, and only a subset of these can bear the cost of what it takes to deliver even a reasonably robust memory solution (there is a reason mainframe-class SMPs are so expensive as it costs a lot to compensate for the inherent availability issues associated with high-component count platforms). Perhaps this will change in the future, but until memory costs drop substantially or a new high-volume, reasonably performant persistent memory media arrives, nothing will change.

I think there is a good chance if it looks like CCIX or Infinity Fabric but is truly open. Imagine the fun we could all have with different kinds of CPUs sharing memory. . . . HA!