Comments on: Aurora In A Socket: What Intel’s “Falcon Shores” XPU Might Do

By: Timothy Prickett Morgan

Timothy Prickett Morgan — Thu, 10 Mar 2022 23:58:10 +0000

In reply to JayN. I suppose it could be. But I was thinking higher up in the memory hierarchy. We are always limited by our initial assumptions.

By: JayN

JayN — Thu, 10 Mar 2022 23:56:08 +0000

“Koduri added that the Falcon Shores XPU would have what he called “extreme bandwidth shared memory,” ”

Why wouldn’t this just be another implementation of the Rambo L2 SRAM ache used on Ponte Vecchio?

One of the recent Intel patent applications shows an entire base layer with embedded sram chiplets. See Fig 32 of US20210150663.

By: Timothy Prickett Morgan

Timothy Prickett Morgan — Thu, 10 Mar 2022 23:48:14 +0000

In reply to JayN. Well, there are three different ways to skin that potential cat, and I just suggested one of them. I guess we will see.

By: JayN

JayN — Thu, 10 Mar 2022 23:36:29 +0000

“There could be an native oneAPI offload across what we presume will be UltraPath Interconnect links between the CPU and GPU parts of the chips, although they could be Xe links.”

I thought a primary feature of cxl is to provide the biased cache coherency, which effectively pools up all the cache coherency transfers while the slave has ownership. Why would they abandon that and return to UPI? Wouldn’t that also require the GPU to have the complicated and proprietary home agent?

By: Timothy Prickett Morgan

Timothy Prickett Morgan — Wed, 02 Mar 2022 00:49:55 +0000

In reply to Venkat S. HA! Yes, Indeed. I also presume not!

By: Venkat S

Venkat S — Wed, 02 Mar 2022 00:44:02 +0000

Hope it isn’t going to consume Aurora (wall) power as well, including cooling power