In my view, compared to ARM, for datacenter use, RISC-V is lagging in its J-extensions for dynamic languages (Java, Python, Javascript, and the likes) — it is a work in progress (challenging) as can be seen here: https://github.com/riscv/riscv-j-extension . Robbin Ehn recently provided an update, at FOSDEM ’24, with respect to OpenJDK, which both provides hope and also shows that the road ahead will be long it seems ( https://fosdem.org/2024/schedule/event/fosdem-2024-2327-unleashing-risc-v-in-managed-runtimes-navigating-extensions-memory-models-and-performance-challenges-in-openjdk/ ).

Meanwhile, even commodity ARM SOCs may include simpler support CPUs to help configure and manage some of their subsystems. The NXP i.MX8MQ (ARMv8, 4xCortex-A53, embedded-focused) for example has an internal Arc CPU to train its LPDDR4 interface, and an Xtensa CPU for configuration of its Cadence HDMI IP. Those types of functions functions could likely be performed by 32-bit integer-core RISC-V as well (IMHO).