Oddly enough, I have been to a kindergarten event where I experienced angst because my child is too chatty sometimes and also had sauerkraut on a frankfurter. HA!

I would be happy to talk abiout Tachyum as soon as they show me a real chip. I still see this ICAm as NextSilicon calls it, as an accelerator. My understanding is Prodigy is an actualy host processor plus accelerator wrapped in one, and like NextSilicon, has a compiler that accelerates the most common routines in code. That was the idea, anyway.

It seems that there’s a lot of interest in using reconfigurable connections between computational units to allow systems to adapt flexibily to workloads that range from “standard flow” (or even no flow) to dataflow. Google’s reconfigurable optical interconnect for TPUs would be a large scale example, while SambaNova’s Reconfigurable Dataflow Units (RDUs), Groq’s Software-defined Scale-out TSP/LPU, or RipTide’s Coarse-Grained Reconfigurable array (CGRA) would be finer scale examples. In my mind, such reconfigurability should mean (as a goal) that the resulting machine performs as well on dense matrix-vector workloads as on graph-oriented workloads (hopefully), through those in-between (HPCG?), by reconfiguring itself accordingly ( https://www.nextplatform.com/2018/08/30/intels-exascale-dataflow-engine-drops-x86-and-von-neuman/ ).

That the compiler (software) is an important aspect of this was certainly stressed by Tenstorrent’s Jim Keller in an excellent interview last year ( https://www.nextplatform.com/2023/08/02/unleashing-an-open-source-torrent-on-cpus-and-ai-engines/ ): “the graph needs to be lowered with interesting software transformations and map that to the hardware”. Here, with NextSilicon’s Maverick, the compiler additionally raises the (reconfigurable) hardware to the graph, which demands some cool extra sophistication (for extra performance), if I understand well.

In time, the reconfigurable NoC between processing units might be advantageously implemented using high-bandwidth reconfigurable optical interposers, with integrated controllers (eg. https://www.eetimes.com/lightmatter-raises-400-million-series-d/ ) … and it should prove worthy to evaluate RAM amounts and distribution, as suggested in the Cerebras article from the day before yesterday, where SwarmX and MemoryX are used to provide supplemental memory where needed (to reap the full benefits of near- and in-memory computing).

Cool stuff!